The above conditions satisfy the Write Propagation criteria required for cache coherence.

If processor P1 reads the old value of X, even after the write by P2, we can say that the memory is incoherent. Propagating the writes to the shared memory location ensures that all the caches have a coherent view of the memory. This condition defines the concept of coherent view of memory. In a read made by a processor P1 to location X that follows a write by another processor P2 to X, with no other writes to X made by any processor occurring between the two accesses and with the read and write being sufficiently separated, X must always return the value written by P2.In a read made by a processor P to a location X that follows a write by the same processor P to X, with no writes to X by another processor occurring between the write and the read instructions made by P, X must always return the value written by P.The following conditions are necessary to achieve cache coherence:

In a multiprocessor system, consider that more than one processor has cached a copy of the memory location X. One type of data occurring simultaneously in different cache memory is called cache coherence, or in some systems, global memory. Definition Ĭoherence defines the behavior of reads and writes to a single address location. However, in practice it is generally performed at the granularity of cache blocks. Theoretically, coherence can be performed at the load/store granularity. Transaction Serialization Reads/Writes to a single memory location must be seen by all processors in the same order. The following are the requirements for cache coherence: Write Propagation Changes to the data in any cache must be propagated to other copies (of that cache line) in the peer caches. Cache coherence is the discipline which ensures that the changes in the values of shared operands (data) are propagated throughout the system in a timely fashion. When one of the copies of data is changed, the other copies must reflect that change. In a shared memory multiprocessor system with a separate cache memory for each processor, it is possible to have many copies of shared data: one copy in the main memory and one in the local cache of each processor that requested it. Cache coherence is intended to manage such conflicts by maintaining a coherent view of the data values in multiple caches.Ĭoherent caches: The value in all the caches' copies is the same. Suppose the client on the bottom updates/changes that memory block, the client on the top could be left with an invalid cache of memory without any notification of the change. In the illustration on the right, consider both the clients have a cached copy of a particular memory block from a previous read. When clients in a system maintain caches of a common memory resource, problems may arise with incoherent data, which is particularly the case with CPUs in a multiprocessing system. In computer architecture, cache coherence is the uniformity of shared resource data that ends up stored in multiple local caches. The aim of this paper is to discuss the efficiency of these protocols in addressing cache coherence problems in multilevel cache technologies.Computer architecture term concerning shared resource data An illustration showing multiple caches of some memory, which acts as a shared resource Incoherent caches: The caches have different values of a single address location. Different protocols have been designed to ameliorate the issues surrounding cache coherence. Cache coherence issues are common problems inherent in this design.

The introduction of multilevel cache technology no doubt speeds up system operations and enhances performance, but is also not without limitations. Multilevel cache is a technological advancement that has made it possible for a multi-core processor system to have more than one cache. Nevertheless, dependence on a single cache for both data and instructions limits the performance of the system regardless of the capacity of the processor and cache size. The cache prevents round-trips to RAM for every memory access. This can be achieved by having, among other system specifications, a high capacity microprocessor and large cache size in a single processor system. The computational tasks of the 21st century require systems with high processing speed.

Cache coherence problems